Об использовании POST кодов для диагностики можно узнать в статье «POST коды».


00Passes control to OS Loader (typically INT19h).
03Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area.
04Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area.
05Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt.
08Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5.
0AInitializes the 8042 compatible Key Board Controller.
0BDetects the presence of PS/2 mouse.
0CDetects the presence of Keyboard in KBC port.
0ETesting and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
13Early POST initialization of chipset registers.
24Uncompress and initialize any platform specific BIOS modules.
30Initialize System Management Interrupt.
2AInitializes different devices through DIM. See DIM Code Checkpoints section of document for more information.
2CInitializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.
2EInitializes all the output devices.
31Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module.
33Initializes the silent boot module. Set the window for displaying text information.
37Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
38Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information.
39Initializes DMAC-1 & DMAC-2.
3AInitialize RTC date/time.
3BTest for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system.
3CMid POST initialization of chipset registers.
40Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, … etc.) successfully installed in the system and update the BDA, EBDA…etc.
50Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.
52Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory.
60Initializes NUM-LOCK status and programs the KBD typematic rate.
75Initialize Int-13 and prepare for IPL detection.
78Initializes IPL devices controlled by BIOS and option ROMs.
7AInitializes remaining option ROMs.
7CGenerate and write contents of ESCD in NVRam.
84Log errors encountered during POST.
85Display errors to the user and gets the user response for error.
87Execute BIOS setup if needed / requested.
8CLate POST initialization of chipset registers.
8DBuild ACPI tables (if ACPI is supported).
8EProgram the peripheral parameters. Enable/Disable NMI as selected.
90Late POST initialization of system management interrupt.
A0Check boot password if installed.
A1Clean-up work needed before booting to OS.
A2Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table.
A4Initialize runtime language module.
A7Displays the system configuration screen if enabled. Initialize the CPU’s before boot, which includes the programming of the MTRR’s.
A8Prepare CPU for OS boot including final MTRR values.
A9Wait for user input at config display if needed.
AAUninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
ABPrepare BBS for Int 19 boot.
ACEnd of POST initialization of chipset registers.
B1Save system context for ACPI.
C0Early CPU Init Start — Disable Cache — Init Local APIC.
C1Set up boot strap proccessor Information.
C2Set up boot strap proccessor for POST.
C5Enumerate and set up application proccessors.
C6Re-enable cache for boot strap proccessor.
C7Early CPU Init Exit.
D0Go to flat mode with 4GB limit and GA20 enabled. Verify the bootblock checksum.
D1Perform keyboard controller BAT test. Check if waking up from power management suspend state. Save power-on CPUID value in scratch CMOS.
D2Disable CACHE before memory detection. Execute full memory sizing module. Verify that flat mode is enabled.
D3If memory sizing module not executed, start memory refresh and do memory sizing in Bootblock code. Do additional chipset initialization.
D4Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
D5Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM.
D6Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. Main BIOS checksum is tested.
D7Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it.
D8The Runtime module is uncompressed into memory. CPUID information is stored in memory.
D9Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write.
DARestore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See POST Code Checkpoints section of document for more information.
E0Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA controller is initialized.
E9Set up floppy controller and data. Attempt to read from floppy.
EAEnable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM. Determine information about root directory of recovery media.
EBDisable ATAPI hardware. Jump back to checkpoint E9.
EFRead error occurred on media. Jump back to checkpoint EB.
F0Search for pre-defined recovery file name in root directory.
F1Recovery file not found.
F2Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.
F3Start reading the recovery file cluster by cluster.
F5Disable L1 cache.
FACheck the validity of the recovery file configuration to the current configuration of the flash part.
FBMake flash write enabled through chipset and OEM specific method. Detect proper flash part. Verify that the found flash part size equals the recovery file size.
F4The recovery file size does not equal the found flash part size.
FCErase the flash part. FD Program the flash part.
FFThe flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h.
00Passes control to OS Loader (typically INT19h).

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